Because miniaturization of elements in integrated circuit electronic devices drives the industry, the width and the pitch of active regions are becoming smaller. Thus, the use of traditional local oxidation of silicon (LOCOS) isolation techniques is gradually replaced by shallow trench isolation (STI). Because it creates relatively little of the bird's beak characteristic, STI is considered to be a more viable isolation technique than LOCOS.
A conventional STI fabrication technique typically comprises: forming a pad oxide on an upper surface of a semiconductor substrate; forming a hardmask layer comprising nitride, such as silicon nitride, having a thickness generally greater than 600 Å, on the semiconductor substrate; forming an opening in the hardmask layer; performing anisotropic etching to form a trench in the semiconductor substrate; forming a thermal oxide liner in the trench and then filling the trench with silicon oxide as an insulating material; and forming an overburden on the hardmask layer. Planarization, such as chemical mechanical polishing (CMP), is then performed. During subsequent processing, the hardmask layer is removed along with the pad oxide, which typically involves cleaning steps. During such cleaning steps, the top corners of the silicon oxide are isotropically removed leaving a void or “divot” in the silicon oxide filled area. This is due to the use of hydrofluoric (HF) acid in the cleaning steps, which partially etches the silicon oxide.
FIG. 1 illustrates an STI structure 12 having divots 16. A dielectric layer 14 is over the substrate 10 and a portion thereof is embedded in the substrate 10. The divots 16 are problematic in various respects. For example, the divots 16 are formed at the trench edges (corners) where high electrical fields are present during device operation and thus cause device degradation including junction leakage and reverse short channel effects. Another drawback in the formation of divots at the STI trench edges is that a divot will trap residual polysilicon and/or metals 18 in subsequent processes, thereby increasing the likelihood of electrical shorting.
Accordingly, what is needed is a method for fabricating an isolation structure being etched by dry chemical having almost no divot.